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| author | Nicolai Hähnle <[email protected]> | 2018-04-12 14:34:19 +0000 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2018-05-15 18:43:49 +0000 |
| commit | 38610f15a7ad7a914e4fd0a9a5a6c386700b8ba0 (patch) | |
| tree | 1625c9be4893e7057a47487dcc9ee8ede676c058 /drivers/gpu/drm/amd/amdgpu/dce_virtual.c | |
| parent | drm/amdgpu: bo could be null when access in vm bo update (diff) | |
| download | kernel-38610f15a7ad7a914e4fd0a9a5a6c386700b8ba0.tar.gz kernel-38610f15a7ad7a914e4fd0a9a5a6c386700b8ba0.zip | |
drm/amdgpu: set COMPUTE_PGM_RSRC1 for SGPR/VGPR clearing shaders
Otherwise, the SQ may skip some of the register writes, or shader waves may
be allocated where we don't expect them, so that as a result we don't actually
reset all of the register SRAMs. This can lead to spurious ECC errors later on
if a shader uses an uninitialized register.
Signed-off-by: Nicolai Hähnle <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Cc: [email protected]
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/dce_virtual.c')
0 files changed, 0 insertions, 0 deletions