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| author | Xin Li (Intel) <[email protected]> | 2025-06-20 23:15:04 +0000 |
|---|---|---|
| committer | Dave Hansen <[email protected]> | 2025-06-24 20:15:52 +0000 |
| commit | fa7d0f83c5c4223a01598876352473cb3d3bd4d7 (patch) | |
| tree | 984f664e2f605c15ae589c47af83d80b8d7f1e0b /drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | |
| parent | x86/traps: Initialize DR6 by writing its architectural reset value (diff) | |
| download | kernel-fa7d0f83c5c4223a01598876352473cb3d3bd4d7.tar.gz kernel-fa7d0f83c5c4223a01598876352473cb3d3bd4d7.zip | |
x86/traps: Initialize DR7 by writing its architectural reset value
Initialize DR7 by writing its architectural reset value to always set
bit 10, which is reserved to '1', when "clearing" DR7 so as not to
trigger unanticipated behavior if said bit is ever unreserved, e.g. as
a feature enabling flag with inverted polarity.
Signed-off-by: Xin Li (Intel) <[email protected]>
Signed-off-by: Dave Hansen <[email protected]>
Reviewed-by: H. Peter Anvin (Intel) <[email protected]>
Reviewed-by: Sohil Mehta <[email protected]>
Acked-by: Peter Zijlstra (Intel) <[email protected]>
Acked-by: Sean Christopherson <[email protected]>
Tested-by: Sohil Mehta <[email protected]>
Cc:[email protected]
Link: https://lore.kernel.org/all/20250620231504.2676902-3-xin%40zytor.com
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h')
0 files changed, 0 insertions, 0 deletions