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| author | Michael Strauss <[email protected]> | 2021-08-11 15:38:44 +0000 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2021-09-01 20:55:10 +0000 |
| commit | bc204778b4032b336cb3bde85bea852d79e7e389 (patch) | |
| tree | 8aaa30aa2eeb42dfbb5cceae88ffb70f9d58c5e2 /drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c | |
| parent | drm/amd/display: Support for DMUB HPD interrupt handling (diff) | |
| download | kernel-bc204778b4032b336cb3bde85bea852d79e7e389.tar.gz kernel-bc204778b4032b336cb3bde85bea852d79e7e389.zip | |
drm/amd/display: Set min dcfclk if pipe count is 0
[WHY]
Clocks don't get recalculated in 0 stream/0 pipe configs,
blocking S0i3 if dcfclk gets high enough
[HOW]
Create DCN31 copy of DCN30 bandwidth validation func which
doesn't entirely skip validation in 0 pipe scenarios
Override dcfclk to vlevel 0/min value during validation if pipe
count is 0
Reviewed-by: Eric Yang <[email protected]>
Acked-by: Qingqing Zhuo <[email protected]>
Signed-off-by: Michael Strauss <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c')
0 files changed, 0 insertions, 0 deletions