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authorChristian König <[email protected]>2022-06-03 13:05:04 +0000
committerAlex Deucher <[email protected]>2022-06-08 15:44:25 +0000
commit64f6516e60b0bbe6abfc9f1d9f1999012e0f11a6 (patch)
tree8c8b59c9340428b5ca12dcee6e6c744bedc0f4f2 /drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c
parentdrm/amdgpu: fix limiting AV1 to the first instance on VCN3 (diff)
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drm/amdgpu: always flush the TLB on gfx8
The TLB on GFX8 stores each block of 8 PTEs where any of the valid bits are set. Fixes: 5255e146c99a ("drm/amdgpu: rework TLB flushing") Reviewed-by: Alex Deucher <[email protected]> Tested-by: Michal Kubecek <[email protected]> Signed-off-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c')
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