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| author | Pierre Yves MORDRET <[email protected]> | 2018-03-13 16:42:04 +0000 |
|---|---|---|
| committer | Vinod Koul <[email protected]> | 2018-04-04 06:19:36 +0000 |
| commit | 80a76952a5a5d2914a5c04d6f3a151348e5580a5 (patch) | |
| tree | 534c4b3597004503d28f1c191eaddf617ed123ae /drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | |
| parent | dmaengine: stm32-dma: fix DMA IRQ status handling (diff) | |
| download | kernel-80a76952a5a5d2914a5c04d6f3a151348e5580a5.tar.gz kernel-80a76952a5a5d2914a5c04d6f3a151348e5580a5.zip | |
dmaengine: stm32-dma: fix max items per transfer
Having 0 in item counter register is valid and stands for a "No or Ended
transfer". Therefore valid transfer starts from @+0 to @+0xFFFE leading to
unaligned scatter gather at boundary. Thus it's safer to round down this
value on its FIFO size (16 Bytes).
Signed-off-by: Pierre-Yves MORDRET <[email protected]>
Signed-off-by: Vinod Koul <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_object.c')
0 files changed, 0 insertions, 0 deletions