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| author | Fangzhi Zuo <[email protected]> | 2023-10-30 20:23:08 +0000 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2023-11-17 14:30:50 +0000 |
| commit | c29085d29562990559163302d9e28d1e88223d90 (patch) | |
| tree | a62e5b21b5854bc2649d89179bab0cb343369198 /drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | |
| parent | drm/amd/display: Send PQ bit in AMD VSIF (diff) | |
| download | kernel-c29085d29562990559163302d9e28d1e88223d90.tar.gz kernel-c29085d29562990559163302d9e28d1e88223d90.zip | |
drm/amd/display: Enable DSC Flag in MST Mode Validation
[WHY & HOW]
When dsc is possible, MST mode validation includes:
1. if maximum dsc compression cannot fit into end to end bw, mode pruned
2. if native bw cannot fit into end to end bw, try to enabled dsc to see
whether a feasible dsc config can be found
3. if native bw can fit into end to end bw, mode supported
Reviewed-by: Wayne Lin <[email protected]>
Acked-by: Alex Hung <[email protected]>
Signed-off-by: Fangzhi Zuo <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c')
0 files changed, 0 insertions, 0 deletions