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| author | Aniruddha Banerjee <[email protected]> | 2018-03-28 13:42:00 +0000 |
|---|---|---|
| committer | Marc Zyngier <[email protected]> | 2018-03-29 10:47:50 +0000 |
| commit | aa08192a254d362a4d5317647a81de6996961aef (patch) | |
| tree | 4078cc6883332ae0fda2dca708cd5ace43a4a354 /drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | |
| parent | irqchip/gic: Update supports_deactivate static key to modern api (diff) | |
| download | kernel-aa08192a254d362a4d5317647a81de6996961aef.tar.gz kernel-aa08192a254d362a4d5317647a81de6996961aef.zip | |
irqchip/gic: Take lock when updating irq type
Most MMIO GIC register accesses use a 1-hot bit scheme that
avoids requiring any form of locking. This isn't true for the
GICD_ICFGRn registers, which require a RMW sequence.
Unfortunately, we seem to be missing a lock for these particular
accesses, which could result in a race condition if changing the
trigger type on any two interrupts within the same set of 16
interrupts (and thus controlled by the same CFGR register).
Introduce a private lock in the GIC common comde for this
particular case, making it cover both GIC implementations
in one go.
Cc: [email protected]
Signed-off-by: Aniruddha Banerjee <[email protected]>
[maz: updated changelog]
Signed-off-by: Marc Zyngier <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c')
0 files changed, 0 insertions, 0 deletions