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| author | Nikunj A Dadhania <[email protected]> | 2025-01-06 12:46:26 +0000 |
|---|---|---|
| committer | Borislav Petkov (AMD) <[email protected]> | 2025-01-07 20:26:06 +0000 |
| commit | 0f0502b8865c0a4c402e73aeb0fb406acc19d0d2 (patch) | |
| tree | ac2403a7ae384732a6c2604301c4f0952462f13b /drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | |
| parent | x86/sev: Add Secure TSC support for SNP guests (diff) | |
| download | kernel-0f0502b8865c0a4c402e73aeb0fb406acc19d0d2.tar.gz kernel-0f0502b8865c0a4c402e73aeb0fb406acc19d0d2.zip | |
x86/sev: Change TSC MSR behavior for Secure TSC enabled guests
Secure TSC enabled guests should not write to the MSR_IA32_TSC (0x10) register
as the subsequent TSC value reads are undefined. On AMD, MSR_IA32_TSC is
intercepted by the hypervisor by default. MSR_IA32_TSC read/write accesses
should not exit to the hypervisor for such guests.
Accesses to MSR_IA32_TSC need special handling in the #VC handler for the
guests with Secure TSC enabled. Writes to MSR_IA32_TSC should be ignored and
flagged once with a warning, and reads of MSR_IA32_TSC should return the
result of the RDTSC instruction.
[ bp: Massage commit message. ]
Suggested-by: Borislav Petkov (AMD) <[email protected]>
Signed-off-by: Nikunj A Dadhania <[email protected]>
Signed-off-by: Borislav Petkov (AMD) <[email protected]>
Reviewed-by: Tom Lendacky <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c')
0 files changed, 0 insertions, 0 deletions