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authorMustapha Ghaddar <[email protected]>2022-11-02 14:14:16 +0000
committerAlex Deucher <[email protected]>2022-11-23 14:47:14 +0000
commitfe4e2662b2ddccd7fa8fc034ed71880626fab279 (patch)
treee6937c5008d728687ba42d3f639f096e50a961c5 /drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
parentdrm/amd/display: Add YCBCR2020 coefficients to CSC matrix (diff)
downloadkernel-fe4e2662b2ddccd7fa8fc034ed71880626fab279.tar.gz
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drm/amd/display: Phase 1 Add Bw Allocation source and header files
[WHY] To implement BW Allocation as per USB4 spec chapter 10.7 [HOW] Implement the DP-Tx portion of the logic to interact with DPIA Reviewed-by: Wenjing Liu <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Brian Chang <[email protected]> Signed-off-by: Mustapha Ghaddar <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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