diff options
| author | Alex Deucher <[email protected]> | 2020-01-08 22:46:02 +0000 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2020-01-14 15:18:09 +0000 |
| commit | 403c1ef0d2cce0be8ab5cf29d9e3d97d587e8582 (patch) | |
| tree | 3b61eaf6fa8ad44421e42be5d7b9c6d62bce44ba /drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | |
| parent | drm/amdgpu/display: set gpu vm flag for all asics which support it (diff) | |
| download | kernel-403c1ef0d2cce0be8ab5cf29d9e3d97d587e8582.tar.gz kernel-403c1ef0d2cce0be8ab5cf29d9e3d97d587e8582.zip | |
drm/amdgpu: enable S/G display on PCO and RV2 (v2)
It should work on all Raven variants, but some users have
reported issues with original Raven with IOMMU enabled.
So far there have been no issues observed with PCO or RV2.
v2: split out the dm init and domain changes into separate
patches.
Acked-by: Harry Wentland <[email protected]>
Acked-by: Huang Rui <[email protected]>
Acked-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_display.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 22 |
1 files changed, 16 insertions, 6 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 4e699071d144..6d520a3eec40 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -513,13 +513,23 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev, * will not allow USWC mappings. * Also, don't allow GTT domain if the BO doens't have USWC falg set. */ - if (adev->asic_type >= CHIP_CARRIZO && - adev->asic_type < CHIP_RAVEN && - (adev->flags & AMD_IS_APU) && - (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) && + if ((bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) && amdgpu_bo_support_uswc(bo_flags) && - amdgpu_device_asic_has_dc_support(adev->asic_type)) - domain |= AMDGPU_GEM_DOMAIN_GTT; + amdgpu_device_asic_has_dc_support(adev->asic_type)) { + switch (adev->asic_type) { + case CHIP_CARRIZO: + case CHIP_STONEY: + domain |= AMDGPU_GEM_DOMAIN_GTT; + break; + case CHIP_RAVEN: + /* enable S/G on PCO and RV2 */ + if (adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8) + domain |= AMDGPU_GEM_DOMAIN_GTT; + break; + default: + break; + } + } #endif return domain; |