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| author | joseph gravenor <[email protected]> | 2019-07-08 17:41:01 +0000 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2019-10-17 20:29:52 +0000 |
| commit | cd83fa1ea9b9431cf1d57ac4179a11bc4393a5b6 (patch) | |
| tree | 1bb389bae9a092b7d960423e727283285bc955af /drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | |
| parent | drm/amd/display: add sanity check for clk table from smu (diff) | |
| download | kernel-cd83fa1ea9b9431cf1d57ac4179a11bc4393a5b6.tar.gz kernel-cd83fa1ea9b9431cf1d57ac4179a11bc4393a5b6.zip | |
drm/amd/display: fix header for RN clk mgr
[why]
Should always MP0_BASE for any register definition from MP per-IP header files.
I belive the reason the linux version of MP1_BASE works is The 0th element of the 0th table
of that is identical to the corrisponding value of MP0_BASE in the renoir offset header file.
The reason we should only use MP0_BASE is There is only one set of per-IP headers MP
that includes all register definitions related to SMU IP block. This IP includes MP0, MP1, MP2
and an ecryption engine that can be used only by MP0. As a result all register definitions from
MP file should be based only on MP0_BASE data.
[How]
Change MP1_BASE to MP0_BASE
Signed-off-by: joseph gravenor <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Reviewed-by: Roman Li <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_device.c')
0 files changed, 0 insertions, 0 deletions