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| author | Rex Zhu <[email protected]> | 2016-11-23 10:09:22 +0000 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2016-12-06 23:08:23 +0000 |
| commit | 3c3a7e616c02cbf0ffcd5888ceffb24e7ac73ad6 (patch) | |
| tree | 59e8742878eef9b3a54379ae6429e17a500f07d4 /drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c | |
| parent | drm/amdgpu: refine uvd 6.0 clock gate feature. (diff) | |
| download | kernel-3c3a7e616c02cbf0ffcd5888ceffb24e7ac73ad6.tar.gz kernel-3c3a7e616c02cbf0ffcd5888ceffb24e7ac73ad6.zip | |
drm/amdgpu: fix bug mclk can't change on Polaris
the root cause is we gate the clock to uvd vcpu.
mclk's change should need the response from uvd if
it is power on.
Signed-off-by: Rex Zhu <[email protected]>
Acked-by: Christian König <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c')
0 files changed, 0 insertions, 0 deletions