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| author | Dmitry Osipenko <[email protected]> | 2019-04-19 11:42:26 +0000 |
|---|---|---|
| committer | Stephen Boyd <[email protected]> | 2019-04-19 22:14:19 +0000 |
| commit | bff1cef5f23afbe49f5ebd766980dc612f5e9d0a (patch) | |
| tree | 1bb8182626caf7d198f9891d55380267458dc4a2 /drivers/fpga/xilinx-spi.c | |
| parent | Linux 5.1-rc1 (diff) | |
| download | kernel-bff1cef5f23afbe49f5ebd766980dc612f5e9d0a.tar.gz kernel-bff1cef5f23afbe49f5ebd766980dc612f5e9d0a.zip | |
clk: tegra: Don't enable already enabled PLLs
Initially Common Clock Framework isn't aware of the clock-enable status,
this results in enabling of clocks that were enabled by bootloader. This
is not a big deal for a regular clock-gates, but for PLL's it may have
some unpleasant consequences. Thus re-enabling PLLX (the main CPU parent
clock) may result in extra long period of PLL re-locking.
Acked-by: Peter De Schrijver <[email protected]>
Signed-off-by: Dmitry Osipenko <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'drivers/fpga/xilinx-spi.c')
0 files changed, 0 insertions, 0 deletions