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| author | Arun Raghavan <[email protected]> | 2025-06-26 13:08:25 +0000 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2025-06-29 21:10:26 +0000 |
| commit | dc78f7e59169d3f0e6c3c95d23dc8e55e95741e2 (patch) | |
| tree | f1c6b2f335f1b8424307587c96028de367bd4139 /drivers/fpga/ts73xx-fpga.c | |
| parent | ASoC: Intel: SND_SOC_INTEL_SOF_BOARD_HELPERS select SND_SOC_ACPI_INTEL_MATCH (diff) | |
| download | kernel-dc78f7e59169d3f0e6c3c95d23dc8e55e95741e2.tar.gz kernel-dc78f7e59169d3f0e6c3c95d23dc8e55e95741e2.zip | |
ASoC: fsl_sai: Force a software reset when starting in consumer mode
On an imx8mm platform with an external clock provider, when running the
receiver (arecord) and triggering an xrun with xrun_injection, we see a
channel swap/offset. This happens sometimes when running only the
receiver, but occurs reliably if a transmitter (aplay) is also
concurrently running.
It seems that the SAI loses track of frame sync during the trigger stop
-> trigger start cycle that occurs during an xrun. Doing just a FIFO
reset in this case does not suffice, and only a software reset seems to
get it back on track.
This looks like the same h/w bug that is already handled for the
producer case, so we now do the reset unconditionally on config disable.
Signed-off-by: Arun Raghavan <[email protected]>
Reported-by: Pieterjan Camerlynck <[email protected]>
Fixes: 3e3f8bd56955 ("ASoC: fsl_sai: fix no frame clk in master mode")
Cc: [email protected]
Reviewed-by: Fabio Estevam <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'drivers/fpga/ts73xx-fpga.c')
0 files changed, 0 insertions, 0 deletions