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| author | Pritam Manohar Sutar <[email protected]> | 2025-05-06 08:01:54 +0000 |
|---|---|---|
| committer | Krzysztof Kozlowski <[email protected]> | 2025-05-12 06:30:06 +0000 |
| commit | 81214185e7e1fc6dfc8661a574c457accaf9a5a4 (patch) | |
| tree | 7125ba3438192baa643fde0dbdc8c495d063dac2 /drivers/fpga/tests/fpga-bridge-test.c | |
| parent | clk: samsung: exynosautov920: Fix incorrect CLKS_NR_CPUCL0 definition (diff) | |
| download | kernel-81214185e7e1fc6dfc8661a574c457accaf9a5a4.tar.gz kernel-81214185e7e1fc6dfc8661a574c457accaf9a5a4.zip | |
clk: samsung: correct clock summary for hsi1 block
clk_summary shows wrong value for "mout_hsi1_usbdrd_user".
It shows 400Mhz instead of 40Mhz as below.
dout_shared2_div4 1 1 0 400000000 0 0 50000 Y ...
mout_hsi1_usbdrd_user 0 0 0 400000000 0 0 50000 Y ...
dout_clkcmu_hsi1_usbdrd 0 0 0 40000000 0 0 50000 Y ...
Correct the clk_tree by adding correct clock parent for
"mout_hsi1_usbdrd_user".
Post this change, clk_summary shows correct value.
dout_shared2_div4 1 1 0 400000000 0 0 50000 Y ...
mout_clkcmu_hsi1_usbdrd 0 0 0 400000000 0 0 50000 Y ...
dout_clkcmu_hsi1_usbdrd 0 0 0 40000000 0 0 50000 Y ...
mout_hsi1_usbdrd_user 0 0 0 40000000 0 0 50000 Y ...
Fixes: 485e13fe2fb6 ("clk: samsung: add top clock support for ExynosAuto v920 SoC")
Cc: <[email protected]>
Signed-off-by: Pritam Manohar Sutar <[email protected]>
Reviewed-by: Alim Akhtar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Diffstat (limited to 'drivers/fpga/tests/fpga-bridge-test.c')
0 files changed, 0 insertions, 0 deletions