clk: update cached phase to respect the fact when setting phase

It's found that the final phase set by driver doesn't match that of
the output from clk_summary:

dwmmc_rockchip fe310000.dwmmc: Successfully tuned phase to 346
mmc0: new ultra high speed SDR104 SDIO card at address 0001

cat /sys/kernel/debug/clk/clk_summary | grep sdio_sample
sdio_sample	0        1        0    50000000 0 0

It seems the cached core->phase isn't updated after the clk was
registered. So fix this issue by updating the core->phase if setting
phase successfully.

Fixes: 9e4d04adeb1a ("clk: add clk_core_set_phase_nolock function")
Cc: Stable <[email protected]>
Cc: Jerome Brunet <[email protected]>
Signed-off-by: Shawn Lin <[email protected]>
Reviewed-by: Jerome Brunet <[email protected]>
Tested-by: Jerome Brunet <[email protected]>
Signed-off-by: Michael Turquette <[email protected]>

0 files changed, 0 insertions, 0 deletions