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| author | Derek Basehore <[email protected]> | 2018-03-13 20:37:19 +0000 |
|---|---|---|
| committer | Heiko Stuebner <[email protected]> | 2018-03-13 23:37:22 +0000 |
| commit | 4ee3fd4abeca30d530fe67972f1964f7454259d6 (patch) | |
| tree | 466579a6610cb0f25a0b836c27dad771367c36aa /drivers/fpga/fpga-region.c | |
| parent | clk: rockchip: Restore the clock phase after the rate was changed (diff) | |
| download | kernel-4ee3fd4abeca30d530fe67972f1964f7454259d6.tar.gz kernel-4ee3fd4abeca30d530fe67972f1964f7454259d6.zip | |
clk: rockchip: Add 1.6GHz PLL rate for rk3399
We need this rate to generate 100, 200, and 228.57MHz from the same
PLL. 228.57MHz is useful for a pixel clock when the VPLL is used for
an external display.
Signed-off-by: Derek Basehore <[email protected]>
Reviewed-by: Douglas Anderson <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]>
Diffstat (limited to 'drivers/fpga/fpga-region.c')
0 files changed, 0 insertions, 0 deletions