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| author | Takeshi Kihara <[email protected]> | 2018-09-28 07:18:00 +0000 |
|---|---|---|
| committer | Geert Uytterhoeven <[email protected]> | 2019-04-02 08:08:29 +0000 |
| commit | 3c772f71a552d343a96868ed9a809f9047be94f5 (patch) | |
| tree | 9ffbab66263db58d02b91dcfa52a86c5cce5e7ab /drivers/fpga/fpga-bridge.c | |
| parent | clk: renesas: rcar-gen3: Correct parent clock of HS-USB (diff) | |
| download | kernel-3c772f71a552d343a96868ed9a809f9047be94f5.tar.gz kernel-3c772f71a552d343a96868ed9a809f9047be94f5.zip | |
clk: renesas: rcar-gen3: Correct parent clock of SYS-DMAC
The clock sources of the AXI BUS clock (266.66 MHz) used for SYS-DMAC
DMA transfers are:
Channel R-Car H3 R-Car M3-W R-Car M3-N
-------------------------------------------------
SYS-DMAC0 S0D3 S0D3 S0D3
SYS-DMAC1 S3D1 S3D1 S3D1
SYS-DMAC2 S3D1 S3D1 S3D1
As a result, change the parent clocks of the SYS-DMAC{1,2} module clocks
on R-Car H3, R-Car M3-W, and R-Car M3-N to S3D1.
NOTE: This information will be reflected in a future revision of the
R-Car Gen3 Hardware Manual.
Signed-off-by: Takeshi Kihara <[email protected]>
[geert: Update RZ/G2M]
Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Simon Horman <[email protected]>
Diffstat (limited to 'drivers/fpga/fpga-bridge.c')
0 files changed, 0 insertions, 0 deletions