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| author | Thorsten Blum <[email protected]> | 2024-10-26 15:53:04 +0000 |
|---|---|---|
| committer | Dinh Nguyen <[email protected]> | 2024-12-17 00:22:00 +0000 |
| commit | ee46245564a8d74ae96394269f173f8306669c04 (patch) | |
| tree | 148c2c4ad33dab2b01a01872e0d73db4a11cf710 | |
| parent | Linux 6.13-rc1 (diff) | |
| download | kernel-ee46245564a8d74ae96394269f173f8306669c04.tar.gz kernel-ee46245564a8d74ae96394269f173f8306669c04.zip | |
clk: socfpga: arria10: Optimize local variables in clk_pll_recalc_rate()
Since readl() returns a u32, the local variable reg can also have the
data type u32. Furthermore, divf and divq are derived from reg and can
also be a u32.
Since do_div() casts the divisor to u32 anyway, changing the data type
of divq to u32 also removes the following Coccinelle/coccicheck warning
reported by do_div.cocci:
WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead
Compile-tested only.
Signed-off-by: Thorsten Blum <[email protected]>
Signed-off-by: Dinh Nguyen <[email protected]>
| -rw-r--r-- | drivers/clk/socfpga/clk-pll-a10.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/socfpga/clk-pll-a10.c b/drivers/clk/socfpga/clk-pll-a10.c index b028f25c658a..62eed964c3d0 100644 --- a/drivers/clk/socfpga/clk-pll-a10.c +++ b/drivers/clk/socfpga/clk-pll-a10.c @@ -35,7 +35,7 @@ static unsigned long clk_pll_recalc_rate(struct clk_hw *hwclk, unsigned long parent_rate) { struct socfpga_pll *socfpgaclk = to_socfpga_clk(hwclk); - unsigned long divf, divq, reg; + u32 divf, divq, reg; unsigned long long vco_freq; /* read VCO1 reg for numerator and denominator */ |