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| author | Ankit Nautiyal <[email protected]> | 2024-04-30 17:28:45 +0000 |
|---|---|---|
| committer | Radhakrishna Sripada <[email protected]> | 2024-05-03 20:15:54 +0000 |
| commit | c528aaa36db031591bfa9d4cb86f23dda4f413b9 (patch) | |
| tree | b4a52d70dbc8f650f058c712033086282b409c46 | |
| parent | drm/i915/bmg: BMG should re-use MTL's south display logic (diff) | |
| download | kernel-c528aaa36db031591bfa9d4cb86f23dda4f413b9.tar.gz kernel-c528aaa36db031591bfa9d4cb86f23dda4f413b9.zip | |
Revert "drm/i915/dgfx: DGFX uses direct VBT pin mapping"
This reverts commit 562f33836f519a235e5c5e71bcc723ab1faccd2f.
For BMG it seems that the VBT to DDI mapping does not follow DG1, and
DG2, but follows ADLP mapping given in Bspec:20124.
Signed-off-by: Ankit Nautiyal <[email protected]>
Signed-off-by: Balasubramani Vivekanandan <[email protected]>
Reviewed-by: Matt Roper <[email protected]>
Signed-off-by: Radhakrishna Sripada <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_bios.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c index 661842a3c2e6..cf770c866d13 100644 --- a/drivers/gpu/drm/i915/display/intel_bios.c +++ b/drivers/gpu/drm/i915/display/intel_bios.c @@ -2231,15 +2231,14 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8 vbt_pin) const u8 *ddc_pin_map; int i, n_entries; - if (IS_DGFX(i915)) - return vbt_pin; - if (INTEL_PCH_TYPE(i915) >= PCH_MTL || IS_ALDERLAKE_P(i915)) { ddc_pin_map = adlp_ddc_pin_map; n_entries = ARRAY_SIZE(adlp_ddc_pin_map); } else if (IS_ALDERLAKE_S(i915)) { ddc_pin_map = adls_ddc_pin_map; n_entries = ARRAY_SIZE(adls_ddc_pin_map); + } else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) { + return vbt_pin; } else if (IS_ROCKETLAKE(i915) && INTEL_PCH_TYPE(i915) == PCH_TGP) { ddc_pin_map = rkl_pch_tgp_ddc_pin_map; n_entries = ARRAY_SIZE(rkl_pch_tgp_ddc_pin_map); |