diff options
| author | Dmitry Baryshkov <[email protected]> | 2025-02-21 15:51:59 +0000 |
|---|---|---|
| committer | Krzysztof Wilczyński <[email protected]> | 2025-02-24 18:29:18 +0000 |
| commit | a22d3039a1d25312ecde0d02bcad4dd235f03e5e (patch) | |
| tree | c2d077a5685c73b7bf3857e9f2d9cf78d88a3c33 | |
| parent | PCI: qcom-ep: Mark BAR0/BAR2 as 64bit BARs and BAR1/BAR3 as RESERVED (diff) | |
| download | kernel-a22d3039a1d25312ecde0d02bcad4dd235f03e5e.tar.gz kernel-a22d3039a1d25312ecde0d02bcad4dd235f03e5e.zip | |
dt-bindings: PCI: qcom-ep: Describe optional dma-coherent property
Qualcomm SA8775P supports cache coherency on the PCIe Endpoint
controller.
Thus, allow "dma-coherent" property to be used for this device. This
fixes a part of the following error (the second part is fixed in the
next commit):
pcie-ep@1c10000: Unevaluated properties are not allowed ('dma-coherent', 'iommus' were unexpected)
Fixes: 4b220c6fa9f3 ("arm64: dts: qcom: sa8775p: Mark PCIe EP controller as cache coherent")
Signed-off-by: Dmitry Baryshkov <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Manivannan Sadhasivam <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <[email protected]>
| -rw-r--r-- | Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index 1226ee5d08d1..0c2ca4cfa3b1 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -91,6 +91,8 @@ properties: - const: pcie-mem - const: cpu-pcie + dma-coherent: true + resets: maxItems: 1 |