diff options
| author | George Shen <[email protected]> | 2021-04-16 21:35:07 +0000 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2021-05-10 22:06:44 +0000 |
| commit | 05e62b6b6433e1159018eb5862e906a3db24dfcd (patch) | |
| tree | c35d2f0b07d1c4523c9b458113281d00785f7379 | |
| parent | drm/amd/display: remove checking sink in is_timing_changed (diff) | |
| download | kernel-05e62b6b6433e1159018eb5862e906a3db24dfcd.tar.gz kernel-05e62b6b6433e1159018eb5862e906a3db24dfcd.zip | |
drm/amd/display: Filter out YCbCr420 timing if VSC SDP not supported
[Why]
Per DP specification, YCbCr420 shall use VSC SDP.
[How]
For YCbCr420 timings, fail DP mode timing validation
if DPCD caps do not indicate VSC SDP colorimetry
support.
Signed-off-by: George Shen <[email protected]>
Reviewed-by: Wenjing Liu <[email protected]>
Acked-by: Wayne Lin <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c index ffb4f9027d5e..ced552ed7b8a 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c @@ -2411,6 +2411,12 @@ bool dp_validate_mode_timing( const struct dc_link_settings *link_setting; + /* According to spec, VSC SDP should be used if pixel format is YCbCr420 */ + if (timing->pixel_encoding == PIXEL_ENCODING_YCBCR420 && + !link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED && + dal_graphics_object_id_get_connector_id(link->link_id) != CONNECTOR_ID_VIRTUAL) + return false; + /*always DP fail safe mode*/ if ((timing->pix_clk_100hz / 10) == (uint32_t) 25175 && timing->h_addressable == (uint32_t) 640 && |