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| author | Gowtham Suresh Kumar <[email protected]> | 2026-07-30 17:10:34 +0200 |
|---|---|---|
| committer | Tomas Mraz <[email protected]> | 2026-09-29 19:00:44 +0200 |
| commit | 0123685f4e01e4b6105087acf393980f200d4f46 (patch) | |
| tree | b442cbf5b05db0b762dd9ac022b2a1330675b74b | |
| parent | Prepare for 3.6.6 (diff) | |
| download | openssl-0123685f4e01e4b6105087acf393980f200d4f46.tar.gz openssl-0123685f4e01e4b6105087acf393980f200d4f46.zip | |
Add support for Arm Neoverse V3AE platform
Add cpu MIDR and ensure relevant optimisations are enabled.
Backport of commit 32ff0eb from master branch.
Signed-off-by: Paul Elliott <[email protected]>
Signed-off-by: Gowtham Suresh Kumar <[email protected]>
Reviewed-by: Tom Cosgrove <[email protected]>
Reviewed-by: Daniel Kubec <[email protected]>
Reviewed-by: Matt Caswell <[email protected]>
Merge-date: Tue Sep 29 16:59:13 2026
Merged-from: https://github.com/openssl/openssl/pull/32125
(cherry picked from commit b108e866388f32a4d0a1ae71d176035426ac8b2a)
| -rw-r--r-- | crypto/arm_arch.h | 1 | ||||
| -rw-r--r-- | crypto/armcap.c | 2 |
2 files changed, 3 insertions, 0 deletions
diff --git a/crypto/arm_arch.h b/crypto/arm_arch.h index 3eb4a884e7e..536d8019506 100644 --- a/crypto/arm_arch.h +++ b/crypto/arm_arch.h @@ -107,6 +107,7 @@ extern unsigned int OPENSSL_armv8_rsa_neonized; #define HISI_CPU_PART_KP920 0xD01 #define ARM_CPU_PART_V2 0xD4F #define ARM_CPU_PART_N3 0xD8E +#define ARM_CPU_PART_V3_AE 0xD83 #define ARM_CPU_PART_V3 0xD84 #define QCOM_CPU_PART_ORYON_X1 0x001 diff --git a/crypto/armcap.c b/crypto/armcap.c index bf1e6db3001..ad5bb389f42 100644 --- a/crypto/armcap.c +++ b/crypto/armcap.c @@ -420,6 +420,7 @@ void OPENSSL_cpuid_setup(void) || MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_MICROSOFT, MICROSOFT_CPU_PART_COBALT_100) || MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_V2) || MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_N3) + || MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_V3_AE) || MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_V3) || MIDR_IMPLEMENTER(OPENSSL_arm_midr) == ARM_CPU_IMP_AMPERE)) OPENSSL_armcap_P |= ARMV8_UNROLL8_EOR3; @@ -427,6 +428,7 @@ void OPENSSL_cpuid_setup(void) if ((OPENSSL_armcap_P & ARMV8_SHA3) && (MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_V1) || MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_V2) + || MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_V3_AE) || MIDR_IS_CPU_MODEL(OPENSSL_arm_midr, ARM_CPU_IMP_ARM, ARM_CPU_PART_V3) || MIDR_IMPLEMENTER(OPENSSL_arm_midr) == ARM_CPU_IMP_AMPERE)) OPENSSL_armcap_P |= ARMV8_UNROLL12_EOR3; |